View IX2120_8567220.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

i ntegrated c ircuits d ivision ds-IX2120-r02 www.ixysic.com 1 driver characteristics features ? floating channel for bootst rap operation to +1200v ? outputs capable of sourcing and sinking 2a ? gate drive supply range from 15v to 20v ? enhanced robustness due to soi process ? tolerant to negative voltage transients: dv/dt immune ? 3.3v logic compatible ? undervoltage lockout for both high-side and low-side outputs description the IX2120 is a high voltage integrated circuit that can drive high speed mosfets and igbts that operate at up to +1200v. the IX2120 is configured with independent high-side and low-side referenced output channels, both of which can source and sink 2a. the floating high-side channel can drive an n-channel power mosfet or igbt 1200v from the common reference. manufactured on ixys integrated circuits division's proprietary high-voltage bcdmos on soi (silicon on insulator) process, the IX2120 is extremely robust, and is virtually immune to negative transients. the uvlo circuit prevents turn-on of the mosfet or igbt until there is sufficient v bs or v cc supply voltage. the IX2120 is available in a 28-pin soic package. ordering information IX2120 functional block diagram parameter rating units v offset 1200 v i o +/- (source/sink) 2/2 a v out 15-20 v t on /t off 250/210 ns part description IX2120b 28-pin soic (28/tube) IX2120btr 28-pin soic (1000/reel) level shift v dd / v cc v ss / com ls delay control level shift v dd / v cc v ss / com uvlo high voltage level shift uvlo pulse generator c r s q buffer v dd hin sd lin v ss v b ho v s v cc lo com input control logic & cycle-by-cycle edge-triggered shutdown buffer mid voltage level shift v bm v sm IX2120 1200v high and low side gate driver
i ntegrated c ircuits d ivision IX2120 2 www.ixysic.com r02 1. specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 package pino u t: 28-pin soic package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 pin description: 28-pin soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 a b sol u te maxim u m ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.5 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.6 dynamic electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.7 static electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.8 test wa v eforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.9 IX2120 typical application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2. typical performance data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3. manufacturing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 moist u re sensiti v ity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 esd sensiti v ity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 soldering profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 board wash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 mechanical dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
i ntegrated c ircuits d ivision IX2120 r02 www.ixysic.com 3 1 specifications typical values are characteristic of the device at + 25c, and are the result of engineering evaluations. they are provided for information purposes only, and are not part of the manufacturing testing requirements. 1.1 package pinout: 28-pin soic package 1.2 pin description: 28-pin soic package v s - 1 8 v b - 2 3 6 7 ho - 4 5 28 9 27 v ss - 14 hin - 11 v dd - 10 lin - 13 sd - 12 15 - lo 16 17 - com 18 19 - v cc 20 21 22 - v sm 23 - v bm 24 - v sm 25 26 pin# name description 1 v s high-side floating supply return 2 v b high-side floating supply 3- no connection 4ho high-side gate drive output 5- no connection 6- no connection 7- internal connection, do not use 8- no connection 9- internal connection, do not use 10 v dd logic supply 11 hi n logic input for high-side gate drive output (ho), in-phase 12 sd logic input for shutdown 13 li n logic input for low-side gate driver output (lo), in-phase 14 v ss logic ground 15 lo low-side gate drive output 16 - no connection 17 com low-side return 18 - no connection 19 v cc low-side supply 20 - internal connection, do not use 21 - no connection 22 v sm middle floating return 23 v bm middle floating supply 24 v sm middle floating return 25 - no connection 26 - no connection 27 - no connection 28 - no connection
i ntegrated c ircuits d ivision 4 www.ixysic.com r02 IX2120 1.3 absolute maximum ratings absolute maximum ratings indicate sustained limits be yond which damage to the device may occur. all voltage parameters are absolute voltages referenced to com. 1.4 thermal characteristics 1.5 recommended operating conditions for proper operation, the device should be used within the recommended conditions. the v s , v sm , and v ss offset ratings are tested with all supplies biased at a 15v differential. parameter symbol min max units high-side floating s u pply v oltage v b -0.3 1400 v high-side floating s u pply offset v oltage v s v b -20 v b +0.3 v high-side floating o u tp u t v oltage v ho v s -0.3 v b +0.3 v middle floating s u pply v oltage v bm -0.3 700 v middle floating s u pply offset v oltage v sm v bm -20 v bm +0.3 v lo w -side fixed s u pply v oltage v cc -0.3 20 v lo w -side o u tp u t v oltage v lo -0.3 v cc +0.3 v logic s u pply v oltage v dd -0.3 v ss +20 v logic s u pply offset v oltage v ss v cc -20 v cc +0.3 v logic inp u t v oltage (hi n , li n , sd) v i n v ss -0.3 v dd +0.3 v allo w a b le offset s u pply v oltage transient d v s /dt -5 0v / n s package po w er dissipation @25c p d -1 . 3w j u nction temperat u re t j -40 +150 c storage temperat u re t s -55 +150 c parameter symbol rating units thermal impedance, j u nction to am b ient ? ja 74 c/w parameter symbol min max units high-side floating s u pply a b sol u te v oltage v b v s +15 v s +20 v high-side floating s u pply offset v oltage v s - 1200 high-side floating o u tp u t v oltage v ho v s v b middle floating s u pply a b sol u te v oltage v bm v sm +15 v sm +20 middle floating s u pply offset v oltage v sm -6 00 lo w -side fixed s u pply v oltage v cc 15 20 lo w -side o u tp u t v oltage v lo 0 v cc logic s u pply v oltage v dd v ss +3 v ss +20 logic s u pply offset v oltage v ss -5 +5 logic inp u t v oltage (hi n , li n , sd) v i n v ss v dd
i ntegrated c ircuits d ivision IX2120 r02 www.ixysic.com 5 1.6 dynamic electrical characteristics v cc , v dd =15v; v bs , v bmsm =13.5v; c l =1000 pf; and v ss =com unless otherwise specified. see ?test waveforms? on page 6 . 1.7 static electrical characteristics v cc , v bmsm , v bs , v dd =15v, and v ss =com unless otherwise specified. the v in , v th , and i in parameters are referenced to v ss and are applicable to all three logic input leads: hin, lin, and sd. the v o and i o parameters are referenced to com and are applicable to the respective output leads: ho or lo. parameter conditions symbol min typ max units t u rn-on propagation delay v s =0 v t on -254- ns t u rn-off propagation delay v sm =600 v v s =1200 v t off -213- sh u tdo w n propagation delay t sd -207- t u rn-on rise time - t r -9.4- t u rn-off fall time - t f -9.7- delay matching, hs & ls t u rn-on/off - mt - - 60 parameter conditions symbol min typ max units logic ?1? inp u t v oltage v dd =15 v v ih 9.5 - - v logic ?0? inp u t v oltage v il --6 logic ?1? inp u t v oltage v dd =3 v v ih 2.5 - - v logic ?0? inp u t v oltage v il --0.8 high-le v el o u tp u t v oltage, v bias - v o i o =0a v oh -1.62.5 v lo w -le v el o u tp u t v oltage, v o i o =20ma v ol - - 0.15 high offset s u pply leakage c u rrent v b = v s =600 v i hlk -3260 ? a middle offset s u pply leakage c u rrent v bm = v sm =600 v i mlk -3260 q u iescent v bs s u pply c u rrent v i n =0 v or v dd i qbs -187310 q u iescent v bmsm s u pply c u rrent v i n =0 v or v dd i qbmsm -487730 q u iescent v cc s u pply c u rrent v i n =0 v or v dd i qcc -300420 q u iescent v dd s u pply c u rrent v i n =0 v or v dd i qdd --1 logic ?1? inp u t bias c u rrent v i n = v dd i in+ -2240 ? a logic ?0? inp u t bias c u rrent v i n =0 v i in- --5 v bs su pply under v oltage positi v e going threshold - v bsuv+ 7.5 8.4 9.7 v v bs su pply under v oltage n egati v e going threshold - v bsuv- 77.89.4 v cc su pply under v oltage positi v e going threshold - v ccuv+ 7.4 8.4 9.6 v cc su pply under v oltage n egati v e going threshold - v ccuv- 77.89.4 o u tp u t high short circ u it p u lsed c u rrent v o =0 v , v i n = v dd , pw ? 10 ? s i o+ 2- - a o u tp u t lo w short circ u it p u lsed c u rrent v o =15 v , v i n =0 v , pw ? 10 ? s i o- 2- -
i ntegrated c ircuits d ivision 6 www.ixysic.com r02 IX2120 1.8 test waveforms 1.8.1 s w itching time test circ u it 1.8.2 inp u t/o u tp u t timing wa v eform 1.8.3 s w itching time wa v eform definition 1.8.4 sh u tdo w n wa v eform definitions 1.8.5 delay matching wa v eform definitions hin sd lin v cc =15v 10 f 0.1f 10f 0.1f 10f c l c l ho lo (0 to 1000v/1200v) v b v s 13.5v + - 15 4 1 21910 11 12 13 14 17 10f 0.1f 10f (0 to 500v/600v) v bm v sm 13.5v + - 23 22 24 v b v dd v cc v ss com v s v bm v sm v sm hin lin sd ho lo hin lin ho lo 50% 50% 90% 90% 10% 10% t on t r t off t f sd ho lo 50% 90% t sd hin lin lo ho 50% 50% 10% 90% mt lo ho mt
i ntegrated c ircuits d ivision IX2120 r02 www.ixysic.com 7 1.9 IX2120 typical application the IX2120 is a 1200v half bridge gate driver for high voltage igbts and mosfets. three input signals (hin, lin, and sd) determine the state of the gate driver outputs (ho and lo). hin controls ho via a high voltage interface. the high voltage interface is integrated into the bootstrap supply by using two 600v diodes (dd1 and dd2). a two-stage bootstrap supplies current to the high side and mid level circuitry. the two bootstrap circuits are identical, and careful board layout and positioning of the bootstrap components are required. resistors rd1 and rd2 form a resistive divider to keep the mid supply very near the center of the high voltage supply range. high value resisters (5m ? ) are recommended to minimize power dissipation. the two-stage bootstrap supply reduces the high side gate drive voltage (v b -v s ) by two diode forward voltage drops (2v f ). therefore, the v cc supply range for the application circuit shown is: where v ce(sat) m2 is the saturation voltage of igbt, m2. the high side bootstrap capacitor selection is a function of the switching frequency and the on-time (t ontime ) of the high side source driver. the quiescent v bs current (i qbs ) is supplied by bootstrap capacitor cb2, and the quiescent v bmsm supply current (i qbmsm ) is supplied by bootstrap capacitor cb1. to insure adequate supply current: and: v dd v ss vhv com m1 1200v m2 1200v dr2 1200v dr1 1200v rb1 5 rb2 5 r12 4.7 r22 4.7 r11 47 r21 47 v s 1 v b 2 n/c 3 ho 4 n/c 5 n/c 6 n/c 7 n/c 8 n/c 9 v dd 10 hin 11 sd 12 lin 13 v ss 14 lo 15 n/c 16 com 17 n/c 1 8 v cc 19 n/c 20 n/c 21 v sm 22 v bm 23 v sm 24 n/c 25 n/c 26 n/c 27 n/c 2 8 IX2120 dg2 25v dg1 25v db1 db2 dd2 600v dd1 600v 600v 600v c1 1 f v cc hin sd lin 25v cb1 0.33 f 25v cb2 0.33 f 25v c3 1 f 25v rd2 5m rd1 5m 20 vv cc v bsuv + 2 v f v ce sat ?? m 2 ++ ?? ?? cb 1 i qbs t ontime v cc v bsuv + 2 vf v ce sat ?? m 2 ++ ?? ? --------------------------------------------------------------------------------------------- ?? cb 2 i qbmsm t ontime v cc v bsuv + 2 vf v ce sat ?? m 2 ++ ?? ? --------------------------------------------------------------------------------------------- ??
i ntegrated c ircuits d ivision 8 www.ixysic.com r02 IX2120 2 typical performance data temperature (oc) -50 -25 0 25 50 75 100 125 turn-off delay time (ns) 0 100 200 300 400 500 turn-off delay time vs. temperature temperature (oc) -50 -25 0 25 50 75 100 125 turn-on delay time (ns) 0 100 200 300 400 500 turn-on delay time vs. temperature supply volta g e (v) 10 12 14 16 1 8 20 turn-on delay time (ns) 0 50 100 150 200 250 300 350 turn-on delay time vs. supply volta g e temperature (oc) -50 -25 0 25 50 75 100 125 shutdown delay time (ns) 0 50 100 150 200 250 300 350 shutdown delay time vs. temperature supply volta g e (v) 10 12 14 16 1 8 20 turn-off delay time (ns) 0 100 200 300 400 500 turn-off delay time vs. supply volta g e temperature (oc) -50 -25 0 25 50 75 100 125 turn-on rise time (ns) 0 10 20 30 40 50 turn-on rise time vs. temperature supply volta g e (v) 0 5 10 15 20 shutdown delay time (ns) 0 50 100 150 200 250 300 350 shutdown delay time vs. v dd supply volta g e temperature (oc) -50 -25 0 25 50 75 100 125 turn-off fall time (ns) 0 10 20 30 40 50 turn-off fall time vs. temperature supply volta g e (v) 10 12 14 16 1 8 20 turn-off fall time (ns) 0 5 10 15 20 25 30 35 turn-off fall time vs. volta g e supply volta g e (v) 10 12 14 16 1 8 20 turn-on rise time (ns) 0 5 10 15 20 25 30 35 turn-on rise time vs. volta g e v dd (v) 0 3 6 9 12 15 1 8 21 log ic ?0? input threshold (v) 0 2 4 6 8 10 12 log ic ?0? input threshold vs. v dd v dd (v) 0 3 6 9 12 15 1 8 21 log ic ?1? input threshold (v) 0 2 4 6 8 10 12 log ic ?1? input threshold vs. v dd
i ntegrated c ircuits d ivision IX2120 r02 www.ixysic.com 9 temperature (oc) -50 -25 0 25 50 75 100 125 log ic "0" input threshold (v) 0 3 6 9 12 15 log ic "0" input threshold vs. temperature temperature (oc) -50 -25 0 25 50 75 100 125 log ic "1" input threshold (v) 0 3 6 9 12 15 log ic "1" input threshold vs. temperature temperature (oc) -50 -25 0 25 50 75 100 125 logic "1" input current (a) 0 20 40 60 80 100 logic "1" input current vs. temperature temperature (oc) -50 -25 0 25 50 75 100 125 logic "0" input current (a) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 logic "0" input current vs. temperature temperature (oc) -50 -25 0 25 50 75 100 125 v dd supply current ( a) 0 5 10 15 20 v dd supply current vs. temperature temperature (oc) -50 -25 0 25 50 75 100 125 v bs supply current ( a) 0 100 200 300 400 500 v bs supply current vs. temperature temperature (oc) -50 -25 0 25 50 75 100 125 v cc supply current ( a) 0 100 200 300 400 500 600 v cc supply current vs. temperature temperature (oc) -50 -25 0 25 50 75 100 125 v bmsm supply current ( a) 0 50 100 150 200 250 300 350 400 450 500 550 v bmsm supply current vs. temperature v cc supply volta g e (v) 10 12 14 16 1 8 20 v cc supply current ( a) 0 100 200 300 400 500 v cc supply current vs. volta g e v dd supply volta g e (v) 0 5 10 15 20 v dd supply current ( a) 0.0 0.2 0.4 0.6 0.8 1.0 v dd supply current vs. volta g e v bs floating supply volta g e (v) 10 12 14 16 1 8 20 v bs supply current ( a) 0 100 200 300 400 500 v bs supply current vs. volta g e v bmsm supply volta g e (v) 10 12 14 16 1 8 20 v bmsm supply current ( a) 0 100 200 300 400 500 600 v bmsm supply current vs. volta g e
i ntegrated c ircuits d ivision 10 www.ixysic.com r02 IX2120 temperature (oc) -50 -25 0 25 50 75 100 125 leaka g e current (a) 0 10 20 30 40 50 hig h/middle supply leaka g e current vs. temperature boost volta g e (v) 0 100 200 300 400 600 leaka g e current (a) 0 100 200 300 400 500 hig h/middle supply leaka g e current vs. v b / v bm volta g e 500 temperature (oc) -50 -25 0 25 50 75 100 125 6 7 8 9 10 11 v ccuv- vs. temperature v ccuv- (v) temperature (oc) -50 -25 0 25 50 75 100 125 v ccuv+ (v) 6 7 8 9 10 11 v ccuv+ vs. temperature temperature (oc) -50 -25 0 25 50 75 100 125 v bsuv+ (v) 6 7 8 9 10 11 v bsuv+ vs. temperature temperature (oc) -50 -25 0 25 50 75 100 125 hig h level output volta g e (v) 0 1 2 3 4 5 hig h level output volta g e vs. temperature (i o =0ma) temperature (oc) -50 -25 0 25 50 75 100 125 v bsuv- (v) 6 7 8 9 10 11 v bsuv- vs. temperature temperature (oc) -50 -25 0 25 50 75 100 125 low level output volta g e (v) 0.0 0.2 0.4 0.6 0.8 1.0 low level output volta g e vs. temperature (i o =20ma) temperature (oc) -50 -25 0 25 50 75 100 125 output sink current (a) 0 1 2 3 4 5 output sink current vs. temperature temperature (oc) -50 -25 0 25 50 75 100 125 output source current (a) 0 1 2 3 4 5 output source current vs. temperature supply volta g e (v) 10 12 14 16 1 8 20 output source current (a) 0 1 2 3 4 5 output source current vs. volta g e supply volta g e (v) 10 12 14 16 1 8 20 output sink current (a) 0 1 2 3 4 5 output sink current vs. volta g e
i ntegrated c ircuits d ivision IX2120 r02 www.ixysic.com 11 supply volta g e (v) 10 12 14 16 1 8 20 hig h level output volta g e (v) 0 1 2 3 4 5 hig h level output volta g e vs. supply volta g e v cc supply volta g e (v) 10 12 14 16 1 8 20 low level output volta g e (mv) 0 40 80 120 160 200 low level output volta g e vs. supply volta g e
i ntegrated c ircuits d ivision 12 www.ixysic.com r02 IX2120 3 manufacturing information 3.1 moisture sensitivity all plastic encapsulated semiconductor packages are susc eptible to moisture ingression. ixys integrated circuits division clas sified all of its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, ipc/jedec j-std-020 , in force at the time of product evaluation. we test all of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our devices when handled according to the limitations and information in that standard as well as to any limitations set forth in the information or standards referenced below. failure to adhere to the warnings or limitations as establ ished by the listed specificati ons could result in reduced product performance, reduction of operable life, and/or reduction of overall reliability. this product carries a moisture sensitivity level (msl) classification as shown below, and should be handled according to the requirements of the latest version of the joint industry standard ipc/jedec j-std-033 . 3.2 esd sensitivity this product is esd sensitive , and should be handled according to the industry standard jesd-625. 3.3 soldering profile provided in the table below is the classification temperature (t c ) of this product and the maximum dwell time the body temperature of this device may be above (t c - 5)oc. the classification temperature sets the maximum body temperature allowed for this device during lead-free reflow processes. for through hole devices, and any other processes, the guidelines of j-std-020 must be observed. 3.4 board wash ixys integrated circuits division recommends the use of no-clean flux formulations. board washing to reduce or remove flux residue following the solder reflow process is acceptable provided proper precautions are taken to prevent damage to the device. these precautions include, but are not limited to: using a low pressure wash and providing a follow up bake cycle sufficient to remove any moisture trapped within the device due to the washing process. due to the variability of the wash parameters used to clean the board, determination of the bake temperature and duration necessary to remove the moisture trapped wit hin the package is the responsibility of the user (assembler). cleaning or drying methods that employ ultrasonic energy may damage the device and should not be used. additionally, the device must not be exposed to flux or solvents that are chlorine- or fluorine-based. device moisture sensitivity level (msl) classification IX2120b msl 1 device classification temperature (t c ) dwell time (t p ) max reflow cycles IX2120b 260c 30 seconds 3
i ntegrated c ircuits d ivision IX2120 r02 www.ixysic.com 13 3.5 mechanical dimensions 3.5.1 IX2120: 28-pin soic package 3.5.2 IX2120 tape & reel information for additional information please visit our website at: www.ixysic.com ixys integrated circuits division makes no representations or wa rranties with respect to the a ccuracy or completeness of the co ntents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. neither circuit patent licenses nor indemnity ar e expressed or implied. except as set forth in ixys integrated circuits division?s standard terms and condit ions of sale, ixys integrated circuits division assumes no liability whatsoever, a nd disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringem ent of any intellectual property right. the products described in this document are not designed, intended, authorized or warranted for use as components in systems in tended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of ixys integrated circuits division?s product may resul t in direct physical harm, injury, or death to a person or severe property or environmental damage. ixys integrated circuits divisi on reserves the right to discontinue or make changes to its pr oducts at any time without notice. specification: ds-IX2120-r02 ?copyright 2016, ixys integrated circuits division all rights reserved. printed in usa. 2/3/2016 17.70 to 18.10 (0.697 to 0.713) see note 3 7.40 to 7.60 (0.291 to 0.299) see note 4 10.00 to 10.65 (0.394 to 0.419) 0.31 to 0.51 28x (0.012 to 0.020) 28x 2.35 to 2.65 (0.093 to 0.104) 1.27 26x (0.05) 26x 0.10 to 0.30 (0.004 to 0.012) 5o to 15o 4x 0.40 to 1.27 (0.016 to 0.050) 0o to 8o 0.20 to 0.33 (0.008 to 0.013) see note 6 0.25 to 0.75 x 45o (0.010 to 0.030) x 45o see note 5 seating plane (min to max inches) min to max mm dimensions 0.10 (0.004) recommended pcb land pattern 9.30 (0.366) 1.27 (0.050) 0.60 (0.024) 2.00 (0.079) notes: 1. all dimensions are in mm / (inches). 2. this package conforms to jedec standard ms-013, variation ae issue c. 3. dimension does not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15mm per end. 4. dimension does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25mm per side. 5. this chamfer is optional. if it is not present, then a pin 1 identifier must be located as shown. 6. the dimension applies to the flat section of the lead between 0.10mm to 0.25mm from the lead tip. pin 1 identifier dimensions mm (inches) top co v er tape thickness 0.102 max (0.004 max) 330.2 dia. (13.00 dia) emb ossed carrier embossment a 0 =10.90 (0.429) b 0 =18.30 (0.720) w=24.00+0.03/-0.01 (0.945+0.001/-0.0004) k 1 =2.70 (0.106) k 0 =3.20 (0.126) p=12.00 (0.472) n otes: 1. unless other w ise specified, all dimensional tolerances per eia standard 481 2. unless other wise specified, all dimensions 0.10 (0.004)

▲Up To Search▲

Price & Availability of IX2120

	To Download IX2120 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .